EI at IPC Printed Circuits Expo, APEX and the Designers Summit 2006

Endicott Interconnect Technologies, Inc., will use the IPC Printed Circuits Expo, APEX and the Designers Summit to showcase its printed circuit board fabrication, advanced electronic semiconductor packaging and 2nd level packaging solutions.

Established quality practices and a keen understanding of manufacturing processes gained through continuous advancements in technology deliver consistent and predictable product quality in printed circuit board fabrication. EI’s offering includes 40+ layer counts, complex backplanes, various via configurations and multiple resin systems. In addition, EI meets ISO, IPC and military specifications, RoHS compliance, ITAR registration and is compatible with lead-free assembly processes.

EI delivers competitive and technical differentiation to customers by providing engineering expertise in advanced processes, product development and manufacturing supporting 1st and 2nd level packaging and assembly solutions. Process capabilities for 1st level packaging using flip chip, wire bond and system-in-package assembly techniques include component placement and related assemblies as well as underfilling, glob top, overmold, coverplate and BGA attach, part marking and test. 2nd level packaging capabilities include prototype development, reliable and flexible manufacturing, in-circuit test development and support, as well as functional and systems test and field service/life cycle management.

EI will also showcase organic semiconductor packaging, providing outstanding field reliability and designed to meet the needs of high performance applications. Semiconductor packaging offerings include HyperBGA, Hyper ZEI, Core EASEI and Wire Bond PBGA.

IPC Printed Circuits Expo, APEX and the Designers Summit takes place at the Anaheim Convention Center, Anaheim, CA, February 8-10, 2006.